There has recently been tremendous growth in the area of digital electronics. The use of digital signals for transmitting and conveying data accurately for storage, reproduction or rendering has steadily increased with advances in digital technology. This growth has occurred in part because digital signals offer many advantages for certain types of design applications. However, since some systems additionally use analog counterparts to digital signals, some applications convert digital signals to analog signals, a continuous time-varying signal, for further processing, for playing of multimedia content, such as sound, or for other reasons. For the case of a single digital input signal, known to have been sampled at a fixed sample rate, conversion of the digital signal to an analog signal can be a relatively straightforward design task. Generally, the designer would implement a digital to analog converter (DAC), a design choice widely recognized by those skilled in the art of circuit design.
Often, however, a system designer, circuit designer or the like may wish for multiple digital input signals to be converted to analog signals. If all of the digital input signals were sampled at the same known sampling rate, the same DAC could be used to convert all of the signals to analog. However, oftentimes there are multiple inputs that have been sampled at different rates. Also, for multi-channel Digital to Analog Converters (DACs), input data to the DAC is currently handled differently depending on the type of DAC employed. For example, in the case of an I2S DAC, input data is applied to the DAC directly after extracting an N*Fs clock from the input signal. Fs is a generic reference understood to refer to sampling frequency by those of ordinary skill in the art. N is generally a positive integer greater than 1, and usually a power of 2, such as 2, 4, . . . 1024, etc. An N*Fs clock signal is thus a signal of higher frequency than the sampling rate of the input signal and is typically used to drive the digital logic of a DAC, other digital logic circuitry and/or the like. In the case of an AC97 DAC, the input is fixed and constrained to a predetermined input frequency, e.g., 48 KHz.
FIG. 1 illustrates a prior art integrated circuit having a multi-channel DAC design. In the case of multiple input sources, sampled at different sampling rates, being applied to a multi-channel I2S DAC chip 10', the I2S DAC chip 10' will have different N*Fs clocks, one for each input source. To clarify, both input i_1 (sampled at a frequency of Fs1) and an N1 *Fs1 clock are input into DAC 200a. Both input i_2 (sampled at a frequency of Fs2) and an N2*Fs2 clock are input into DAC 200b, and so on. The parameter N is a parameter that is well known to those of ordinary skill in the art of circuit design, and its choice depends upon the circuitry for which it will be used. In this regard, different DACs can each have a different N associated therewith. Basing conversion on the N1*Fs1 clock input, DAC 200a converts digital input i_1 to analog output o_1. In a similar manner, basing conversion on the N2*Fs2 clock input, DAC 200b converts digital input i_2 to analog output o_2, and so on. In this fashion, n different analog outputs are produced from n different digital inputs using n different N*Fs clocks.
The implementation of n different N*Fs clocks, however, can cause difficulties, particularly when all of the circuitry is implemented on a single chip or integrated circuit 10'. The use of multiple N*Fs clocks, for example, can degrade the overall performance of the DAC. For instance, due to ground bounce, cross-talk, interference and/or the like, a disturbance in the electrical integrity of a ground plane, input signal, output signal, or power source may result. If this occurs, performance can decrease and the probability that spurious noise will superpose or otherwise interfere with the output increases.
Traditional efforts at solving these problems relating to multiple channel DAC design have involved attempts at eliminating the effects of multiple clocks during the layout phase of the chip or device. Designers have attempted to implement guard rings or extra isolation circuitry to eliminate or reduce the effects of the above problems. The provision of independent ground planes can also be of help, but further adds to the difficulties and costs of design. Further, these solutions can not ensure that the electrical integrity of the output signals will be maintained. Also, even an experienced layout artist may not appreciate the extra constraints being placed on the design process. Every new design contraint places a burden on the overall design process, and thus it is desirable to place as few contraints on a design as possible.
The above prior art chip design employed n different N*Fs clocks, which creates a whole set of associated problems, as noted above. An alternative proposed solution has been to use the same clock input, or no clock input in the case of a DAC with an internal clock, and to regulate the input to meet certain input requirements. Namely, the inputs have to meet the requirement that they were all sampled at the same rate. In the case of an AC97 DAC, the inputs are fixed and constrained to an input frequency of 48 KHz. As a result, however, there is a clear loss in the area of design flexibility. Inputs generally do not conform to a fixed sampling rate, especially when the inputs come from different sections of a system and are used for different purposes. Additional components may be added to cause the inputs to conform to the requirements of such a DAC. However, these extra components only add to the cost of a design. Also, these components would inherently be positioned off chip, since a DAC chip manufacturer can not anticipate the sampling rates of various inputs of a system not yet designed.
Consequently, it would be advantageous to provide a multi-channel DAC integrated circuit capable of converting digital inputs sampled at different sampling rates to analog signals, without regard to input sampling rates, that solves the above problems. It would be further advantageous to provide on chip pre-processing of the input signals that addresses the differences in sampling rates, so that one clock can be used for multiple DACs.